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Features
ARM7TDMI(R) ARM(R) Thumb(R) Processor Core One 16-bit Fixed-point OakDSPCore(R) Core Dual Ethernet 10/100 Mbps MAC Interface with Voice Priority Multi-layer AMBATM Architecture 256 x 32-bit Boot ROM 88K Bytes of Integrated Fast RAM Flexible External Bus Interface with Programmable Chip Selects Codec Interface Multi-level Priority, Individually Maskable, Vectored Interrupt Controller Three 16-bit Timers/Counters Additional Watchdog Timer Two USARTs with FIFO and Modem Control Lines Industry Standard Serial Peripheral Interface (SPI) Up to 24 General-purpose I/O Pins On-chip SDRAM Controller for Embedded ARM7TDMI and OakDSPCore JTAG Debug Interface 2.5V Power Supply for the Core and the PLL Pins, 3.3V for Other I/O Pins Software Development Suites Available for ARM7TDMI and OakDSPCore Supported by a Wide Range of Ready-to-use Application Software, Including Multitasking Operating System, Networking and Voice Processing Functions * Available in a 208-lead PQFP Package
* * * * * * * * * * * * * * * * * * *
Smart Internet Appliance Processor (SIAPTM) AT75C220 Preliminary
Description
The AT75C220, Atmel's device in the family of smart Internet appliance processors (SIAP), is a high-performance processor specially designed for professional Internet appliance applications, such as the Ethernet IP phone. The AT75C220 is built around an ARM7TDMI microcontroller core running at 40 MIPS with an OakDSPCore co-processor running at 60 MIPS and a dual-port Ethernet 10/100 Mbps MAC interface. In a typical standalone IP phone, the DSP handles the voice processing functions (voice compression, acoustic echo cancellation, etc.), while the dual-port Ethernet 10/100 Mbps MAC interface establishes the connection to the Ethernet physical layer (PHY), which links the network and the PC. In such an application, the power of the ARM7TDMI allows it to run a VoIP protocol stack as well as all the system control tasks. Atmel provides the AT75C220 with three levels of software modules: * * * A special port of the Linux kernel as the proposed operating system A comprehensive set of tunable DSP algorithms for voice processing, specially tailored to be run by the DSP subsystem A broad range of application level software modules such as H323 telephony or POP-3/SMTP e-mail services
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AT75C220 Pin Configuration
Table 1. AT75C220 Pin Configuration
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal GND SCLKA VDD3V3 FSA STXA SRXA NTRST MA_COL MA_CRS MA_TXER MA_TXD<0> MA_TXD<1> MA_TXD<2> MA_TXD<3> MA_TXEN VDD3V3 MA_TXCLK GND MA_RXD<0> MA_RXD<1> MA_RXD<2> MA_RXD<3> MA_RXER MA_RXCLK GND VDD2V5 MA_RXDV MA_MDC MA_MDIO MA_LINK MB_COL MB_CRS GND VDD2V5 VDD3V3 MB_TXER MB_TXD<0> MB_TXD<1> MB_TXD<2> GND MB_TXD<3> MB_TXEN Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Signal MB_TXCLK MB_RXD<0> MB_RXD<1> MB_RXD<2> MB_RXD<3> MB_RXER MB_RXCLK MB_RXDV MB_MDC VDD3V3 GND MB_MDIO MB_LINK A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> A<8> A<9> A<10> A<11> A<12> VDD3V3 GND A<13> A<14> A<15> A<16> A<17> A<18> A<19> A<20> A<21> D<0> D<1> D<2> D<3> GND Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Signal D<4> VDD3V3 D<5> D<6> D<7> D<8> D<9> D<10> D<11> D<12> D<13> D<14> VDD2V5 GND D<15> VDD3V3 GND NREQ NGNT VDD3V3 GND DCK CS0 CS1 RAS CAS NC WE DQM<0> DQM<1> DQM<2> GND DQM<3> VDD2V5 GND PLL_VDD XREF240 PLL_GND GND XTALOUT XTALIN VDD2V5 Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Signal NCE0 NCE1 NCE2 VDD3V3 NCE3 NWE0 NWE1 NWE2 VDD3V3 GND NWE3 NWR NSOE GND VDD2V5 NWAIT MISO MOSI SPCK NPCSS VDD3V3 GND RESET FIQ IRQ<0> TST GND VDD2V5 NC VDD3V3 GND VDD3V3 TDO TDI TMS TCK PA<19> VDD2V5 GND PA<12> GND VDD3V3 Pin 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal PA<11> PA<10> PA<9> PA<8> PA<7> PA<6> VDD3V3 NC PA<5> PA<4> PA<3> PA<2> PA<1> PA<0> GND RXDA TXDA NRTSA NCTSA NDTRA NDSRA NDCDA RXDB TXDB GND PB<0> PB<1> PB<2> PB<3> PB<4> PB<5> PB<6> PB<7> PB<8> PB<9> VDD3V3 DBW32 GND BO256 VDD3V3
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Table 2. AT75C220 Pin Description List
Block Common Bus Pin Name A[21:0] D[15:0] NREQ NGNT Synchronous Dynamic Memory Controller DCLK DQM[1:0] CS0 CS1 RAS CAS WE Static Memory Controller NCE0, NCE3 NWE[1:0] NSOE NWR NWAIT I/O Port A PA[12:0] PA[19] I/O Port B DSP Subsystem PB[9:0] OAKAIN[1:0] OAKAOUT[1:0] Timer/Counter 0 TCLK0 TIOA0 TIOB0 Timer/Counter 1 TCLK1 TIOA1 TIOB1 Watchdog Serial Peripheral Interface NWDOVF MISO MOSI SPCK NPCSS NPCS1 Function Address Bus Data Bus Bus Request Bus Grant SDRAM Clock SDRAM Byte Masks SDRAM Chip Select 0 SDRAM Chip Select 1 Row Address Strobes Column Address Strobes SDRAM Write Enable Chip Selects Byte Select/Write Enable Output Enable Memory Block Write Enable Enable Wait States General-purpose I/O lines. Multiplexed with peripheral I/Os. General-purpose I/O line. Multiplexed with peripheral I/Os. General-purpose I/O lines. Multiplexed with peripheral I/Os. OakDSPCore User Input OakDSPCore User Output Timer 0 External Clock Timer 0 Signal A Timer 0 Signal B Timer 1 External Clock Timer 1 Signal A Timer 1 Signal B Watchdog Overflow Master In/Slave Out Master Out/Slave In Serial Clock Chip Select/Slave Select Optional SPI Chip Select 1 Type Output Input/Output Input Output Output Output Output Output Output Output Output Output Output Output Output Input Input/Output Input/Output Input/Output Input Output Input Input/Output Input/Output Input Input/Output Input/Output Output Input/Output Input/Output Input/Output Input/Output Output
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Table 2. AT75C220 Pin Description List (Continued)
Block USART A Pin Name RXDA TXDA NRTSA NCTSA NDTRA NDSRA/BOOTN NDCDA USART B RXDB TXDB JTAG Interface NTRST TCK TMS TDI TDO Codec Interface SCLKA FSA STXA SRXA MAC A Interface MA_COL MA_CRS MA_TXER MA_TXD[3:0] MA_TXEN MA_TXCLK MA_RXD[3:0] MA_RXER MA_RXCLK MA_RXDV MA_MDC MA_MDIO MA_LINK Function Receive Data Transmit Data Ready to Send Clear to Send Data Terminal Ready Data Set Ready Data Carrier Detect Receive Data Transmit Data Test Reset Test Clock Test Mode Select Test Data Input Test Data Output Serial Clock Frame Pulse Transmit Data to Codec Receive Data to Codec MAC A Collision Detect MAC A Carrier Sense MAC A Transmit Error MAC A Transmit Data Bus MAC A Transmit Enable MAC A Transmit Clock MAC A Receive Data Bus MAC A Receive Error MAC A Receive Clock MAC A Receive Data Valid MAC A Management Data Clock MAC A Management Data Bus MAC A Link Interrupt Type Input Output Output Input Output Input Input Input Output Input Input Input Input Output Input/Output Input/Output Input Output Input Input Output Output Output Input Input Input Input Output Output Input/Output Input
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Table 2. AT75C220 Pin Description List (Continued)
Block MAC B Interface Pin Name MB_COL MB_CRS MB_TXER MB_TXD[3:0] MB_TXEN MB_TXCLK MB_RXD[3:0] MB_RXER MB_RXCLK MB_RXDV MB_MDC MB_MDIO MB_LINK Miscellaneous RESET FIQ/LOWP IRQ0 XREF240 XTALIN XTALOUT TST B0256 DBW32 Function MAC B Collision Detect MAC B Carrier Sense MAC B Transmit Error MAC B Transmit Data Bus MAC B Transmit Enable MAC B Transmit Clock MAC B Receive Data Bus MAC B Receive Error MAC B Receive Clock MAC B Receive Data Valid MAC B Management Data Clock MAC B Management Data Bus MAC B Link Interrupt Power on Reset Fast Interrupt/Low Power External Interrupt Requests External 240 MHz PLL Reference External Crystal Input External Crystal Ouptut Test Mode Package Size Option (1 = 256 pins) External Data Bus Width for CS0 (1 = 32 bits) Type Input Input Output Output Output Input Input Input Input Output Output Input/Output Input Input Input Input Input Input Output Input Input Input
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Block Diagram
Figure 1. AT75C220 Block Diagram
Dual Ethernet 10/100 Mbps MAC Interface
ASB
Reset
OakDSPCore DSP Subsystem
Clocks
JTAG
SDRAM Controller External Bus Interface
Embedded ICE
SRAM Controller
ARM7TDMI Core
Boot ROM
Peripheral Data Controller
AMBA Bridge SPI IRQ Controller USART 0 PIO 0 USART 1 PIO 1 Timer/Counter 0 Timer/Counter 1 Watchdog Timer Timer/Counter 2
APB
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Figure 2. DSP Subsystem Block Diagrams
Oak Program Bus
2K x 16 X-RAM Codec Interface 2K x 16 Y-RAM
Oak Data Bus
24K x 16 Program RAM
OakDSPCore
16K x 16 Generalpurpose RAM
On-chip Emulation Module
256 x 16 Dual-port Mailbox
Bus Interface Unit
DSP Subsystem
ASB
Application Example
Figure 3. Standalone Ethernet Telephone
Keyboard Screen
Network
Ethernet 10/100 Mbps PHY Ethernet 10/100 Mbps PHY Speaker Phone Interface
PC Speaker Microphone Handset
Dual-port Ethernet 10/100 Mbps MAC Interface
SDRAM Controller VolP Protocol Stack
SDRAM
External Bus Interface
Voice Codec
Voice Processing
DSP Subsystem
SRAM Controller ARM7TDMI Core
Analog Front End
Flash
AT75C220
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Functional Description
ARM7TDMI Core
The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16-bit wide and give maximum code density. Instructions operate on 8-bit, 16-bit and 32-bit data types. The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including six status registers.
DSP Subsystem
The AT75C220 DSP subsystem is composed of: * * * * * * * An OakDSPCore running at 60 MIPS 2K x 16 of X-RAM 2K x 16 of Y-RAM 16K x 16 of general purpose data RAM 24K x 16 of loadable program RAM One 256 x 16 dual-port mailbox One codec interface
The DSP subsystem is fully autonomous. The local X- and Y-RAM allows it to reach its maximum processing rate, and a local large data RAM enables complex DSP algorithms to be implemented. The large size of the loadable program RAM permits the use of functions as complex as a low bit-rate vocoder. During boot time, the ARM7TDMI core has the ability to maintain the OakDSPCore in reset state and to upload DSP code. When the OakDSPCore reverts to an active state, this code is executed. When the OakDSPCore is running the dual-port mailbox is used as the communication channel between the ARM7TDMI and the OakDSPCore. A programmable codec interface is directly connected to the OakDSPCore. It allows the connection of most industrial voice, multimedia or data codecs.
Ethernet MAC
The AT75C220 contains an Ethernet subsystem specially designed to cope with the VoIP application requirements. It is mainly composed of three independent parts: two identical independent Ethernet MACs and a packet buffer of 32K bytes, connected together with a local bus. The major benefit provided by two separate Ethernet MACs is the possibility to deploy VoIP Ethernet telephony without re-wiring buildings. The Ethernet MACs exhibit the following features: * * * * * * Support for 10 and 100 Mbps operation Support for full- and half-duplex Standard MII interface Broadcast, multicast and four unicast address filters Automatic CRC generation Automatic zero padding
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* * * Pause and jamming support Transmit and receive FIFOs Integrated DMA
The local packet buffer is filled/emptied by the MACs' DMA. This memory is used to store the received/transmitted packets temporarily. Its size allows it to hold enough packets to cope with most situations. Should an overflow occur, a part of the external system memory can be used as an overflow buffer to avoid data loss. The main benefit of having a local bus is that the majority of packets can be received from one MAC and transmitted through the other without software intervention.
Boot ROM
Boot Code Operation
The ARM7TDMI has the ability to boot either from an external memory or from the on-chip 256 x 32-bit boot ROM. The internal boot sequence allows programming of the ARM7TDMI program RAM through a serial port. When the download is complete, a branch is executed to the downloaded code. The EBI generates the signals which control access to external memory or memory-mapped peripherals. The EBI is fully programmable and can address up to 64M bytes. The interface to external devices is composed of common address and data buses and separate control lines to allow the connection of static or dynamic devices. The main features are: * * * * * * * * * * External memory mapping Up to four chip select lines 32- or 16-bit data bus Byte write or byte select lines Remap of boot memory Support for both static and dynamic memories Two different read protocols for static memories Support for early read/early write for dynamic memories Programmable wait state generation Programmable data float time
EBI: External Bus Interface
AIC: Advanced Interrupt Controller
The AT75C220 has an 8-level priority interrupt controller. The interrupt controller outputs are connected to the fast interrupt request (NFIQ) and the normal interrupt request (NIRQ) of the ARM7TDMI core. The processor's NFIQ can only be asserted by the external fast interrupt request input (FIQ). The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals or by the external interrupt request line IRQ0. An 8-level priority encoder allows the application to define the priority between the different interrupt sources. Interrupt sources are programmed to be level sensitive or edge sensitive. External sources can be programmed to be positive- or negative-edge triggered, or low- or high-level sensitive.
PIO: Parallel I/O Controller
The AT75C220 has 24 programmable I/O lines. They can all be programmed as inputs or outputs. To optimize the use of available package pins, most of them are multiplexed with external signals of on-chip peripherals. The PIO lines are controlled by two separate and identical PIO controllers called PIOA and PIOB.
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The PIO controllers enable the generation of an interrupt on input change on each PIO line. Some I/O lines have enough drive capability to power a LED.
USART: Universal Synchronous/ Asynchronous Receiver/ Transmitter
The AT75C220 provides two identical full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: * * * * * * * * Programmable baud rate generator Parity, framing and overrun error detection Line break generation and detection Automatic echo, local loopback and remote loopback Multi-drop mode: address detection and generation Interrupt generation Dedicated peripheral data controller channels 6-, 7- and 8-bit character length
Additionally to the Tx and Rx signals, the USART A provides several modem control lines.
SPI: Serial Peripheral Interface
The AT75C220 includes an SPI which provides communication with external devices in master or slave mode. The SPI has one external chip select which can be connected to up to 2 devices. The data length is programmable from 8- to 16-bit. The AT75C220 features three identical 16-bit timer/counters. They can be independently programmed to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. The triple timer/counter block has three external clock inputs, five internal clock inputs and two multi-purpose signals which can be configured by the user. Each timer drives an internal interrupt signal which can be programmed to generate processor interrupts via the Advanced Interrupt Controller.
Timer/Counter
Watchdog Timer Special Functions
The AT75C220 has an internal Watchdog Timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock. The AT75C220 provides registers which implement the following special functions: * * * Chip identification Reset status Power management
Application Software
The AT75C220 is supported by a comprehensive range of software modules. As a result of the widespread use of the ARM7TDMI and the OakDSPCore, a wide range is available directly from Atmel, from Atmel's qualified software partner or from other third parties. The application software modules are in three categories: OS, DSP and application levels.
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OS Level The AT75C220 is supplied with a customized port of the Linux kernel. It features device drivers for all the on-chip peripherals, including the DSP subsystems, and supports virtual file system usage. It also supports the native TCP/IP facilities which have made Linux a success in Internet applications. This kernel is available in source code under the terms of the Gnu Public License. Many other operating systems exist for the ARM7TDMI core. DSP Level A wide range of digital signal processing functions is available for the OakDSPCore. Amongst others, Atmel supplies modules for G723.1 and G729A voice codecs, silence compression and echo cancellation. Many third parties also provide ready-to-use libraries for the OakDSPCore. Application Level A rich software toolkit is available with support for popular communication protocols (H323, POP-3/SMTP, etc.), connection processes, multimedia applications, full-feature telephony and audio software suites. Both the ARM7TDMI and the OakDSPCore are industry-standard cores. They are supported by a comprehensive range of state-of-the-art development tools, including assemblers, Ccompilers, source level debuggers and hardware emulators. The AT75C220 is supplied in a 208-lead PQFP package. This provides the best compromise between external connectivity and cost. An alternative 256-ball PBGA package is also available. In addition to a larger I/O capability, it provides the application developer with the possibility of using advanced development tools for the DSP subsystem software. Although this 256-ball PBGA package is more dedicated to development, it can also be used in production for systems which require a high level of connectivity: it offers up to 48 generalpurpose I/Os and a full-width system bus (24 address bits and 32 data bits).
Development Tools Packaging
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Figure 4. PQFP Package Drawing
C
C
1
For package data, see Table 3, Table 4 and Table 5 below.
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Package Data
Table 3. Dimensions (mm)
Symbol c c1 L L1 R2 R1 S Tolerances of Form and Position aaa ccc 0.25 0.10 0.13 0.13 0.4 Min 0.11 0.11 0.65 0.15 0.88 1.60 REF 0.3 Nom Max 0.23 0.19 1.03
Table 4. Dimensions specific to 208-lead Package (mm)
A Max 4.10 A1 Min 0.25 Min 3.20 A2 Nom 3.40 Max 3.60 Min 0.17 b Max 0.27 Min 0.17 b1 Nom 0.20 Max 0.23 D BSC 31.20 D1 BSC 28.00 E BSC 31.20 E1 BSC 28.00 e BSC 0.50 ddd BSC 0.10
Table 5. 208-lead PQFP Package Electrical Characteristics
Body Size 28 x 28 R (m) Min 53 Max 71 Min 1.4 Cs (pF) Max 1.7 Min 0.56 Cm (pF) Max 0.73 Min 6.7 Ls (nH) Max 8.4 Min 3.9 Lm (nH) Max 5.1
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(c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ARM, ARM7TDMI, AMBA, ARM Powered and Thumb are trademarks of ARM Limited. OakDSPCore is a trademark of DSP Group, Inc. SIAP is a trademark of Atmel Corporation. Linux is a trademark of Linus Torvalds. Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
Rev. 1396BS-03/01

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